1. Field of the Invention
The present invention relates to a method of rewriting a boot program that is executed by a CPU to start a radio communication device such as a cellular phone unit or the like, and more particularly to a radio communication device and a method of rewriting a boot program which allow a rewritten boot program to be executed reliably.
2. Description of the Related Art
Cellular phone units that are available in recent years have additional functions including a mail function, a web function, a game function, etc. in addition to a conventional telephonic communication function, and need to perform complex software processing capabilities.
Some cellular phone units with such multiple functions have two CPUs, i.e., a CPU (hereinafter referred to as “communication core”) for processing baseband signals with CODEC and performing a communication protocol control process between themselves and radio base stations, and a CPU (hereinafter referred to as “control core”) for controlling displays, key operations, and other additional functions.
FIG. 1 of the accompanying drawings shows in block form a conventional cellular phone unit having two CPUs.
As shown in FIG. 1, conventional cellular phone unit 1300 has CPUs 1311, 1321, ROMs 1312, 1322, RAMs 1313, 1323, port interfaces 1314, 1324, and port switch 1301, and can be connected to personal computer (PC) 1310.
CPU 1311, ROM 1312, RAM 1313, and port interface 1314 are connected to each other by address and data lines 1315 of CPU 1311. CPU 1321, ROM 1322, RAM 1323, and port interface 1324 are connected to each other by address and data lines 1325 of CPU 1321.
CPU 1311 and CPU 1321 are processors that operate independently of each other, one serving as a communication core and the other a control core.
Programs that are executed by CPU 1311 is stored in ROM 1312. CPU 1311 temporarily uses RAM 1313 when it runs various programs.
Port interface 1314 controls port 1316 in order to allow communications between CPU 1311 and PC 1310.
Programs that are executed by CPU 1321 is stored in ROM 1322. CPU 1321 temporarily uses RAM 1323 when it runs various programs.
Port interface 1324 controls port 1326 in order to allow communications between CPU 1321 and PC 1310.
Port switch 1301 is instructed by PC 1310 to select either CPU 1311 or CPU 1321 and connect the selected CPU to PC 1310.
In devices incorporating a CPU therein, programs that are executed by the CPU are generally stored in a ROM. Recently, progresses in the electronic device technology make it possible to increase the storage capacity of devices capable of holding and rewriting recorded data without a power supply, such as a EEPROM (Electrically Erasable Programmable ROM) and an FROM (Flash ROM). Therefore, EEPROMs or FROMs are finding more applications than ordinary ROMs. ROMs 1312, 1322 shown in FIG. 1 comprise a ROM where recorded contents can be rewritten, such as an EEPROM or an FROM.
Generally, a program which is executed when a CPU is started is called a boot program. The boot program for CPU 1311 is stored in a particular area in ROM 1312, and the boot program for CPU 1321 is stored in a particular area in ROM 1322. When CPUs 1311, 1321 are started, they access the particular areas in ROMs 1312, 1322, respectively, and execute the boot programs stored therein.
If the boot program for CPU 1311 is to be changed due to a bug or an added or changed function, PC 1310 writes a new boot program into ROM 1312. Specifically, PC 1310 controls port switch 1301 to select port 1316, and transmits the new boot program to CPU 1311. CPU 1311 receives and writes the new boot program into the particular area in ROM 1312.
At this time, CPU 1311 may be running a program for usual operation (referred to as “on-line mode”) or may be running a program for communicating with PC 1310 while stopping usual operation (referred to as “off-line mode”). In order for CPU 1311 to receive the boot program from PC 1310 in the on-line mode, the program for usual operation needs to have a process for communicating with PC 1310. In order for CPU 1311 to receive the boot program from PC 1310 in the off-line mode, an off-line program having a process for communicating with PC 1310 needs to be stored in ROM 1312 in a manner to be executable by CPU 1311.
Alternatively, conventional cellular phone unit 1300 may be arranged to write the boot program from PC 1310 directly into ROM 1312, not through CPU 1311. In this case, port interface 1314 acts as a bus master for address and data lines 1315.
When CPU 1311 is to be restarted after the boot program has been rewritten, CPU 1311 reads and executes the new boot program, and is started, confirming that the boot program has properly been changed.
The boot program for CPU 1321 may also be changed in the same manner as with the boot program for CPU 1311.
Japanese laid-open patent publications Nos. 8-179937 and 2000-293376 disclose boot program rewriting devices having a plurality of boot program areas which can easily be changed without complex operations.
FIG. 2 of the accompanying drawings shows in block form a conventional boot program rewriting device disclosed in Japanese laid-open patent publication No. 8-179937. The conventional boot program rewriting device shown in FIG. 2 has CPU 1401, resetting unit 1402, address decoder 1403, ROMs 1404a through 1404d, normal boot monitor unit 1405, reset switch 1406, and display LED 1407. It is assumed that the addresses of ROMs 1404a through 1404d are mapped in the order of ROM 1404a, ROM 1404b, ROM 1404c, and ROM 1404d. 
CPU 1401 is started by boot programs stored in ROMs 1404a through 1404d. Addresses of the boot programs are input to ROMs 1404a through 1404d by low-order bits of address signal 1408.
Address decoder 1403 decodes high-order bits of address signal 1408 and generates chip select signals 1412a through 1412d. When accessed by CPU 1401, either one of ROMs 1404a through 1404d is selected by chip select signals 1412a through 1412d. 
Resetting unit 1402 monitors a power supply voltage and reset switch 1406. When the power supply voltage drops or reset switch 1406 is operated, resetting unit 1402 generates a reset pulse of given duration. The reset pulse acts as CPU resetting signal 1409 and also as address decoder resetting signals 1410, 1411 for controlling the chip selection of address decoder 1403. Address decoder resetting signal 1410 is a resetting signal generated based on the monitoring of the power supply voltage. Address decoder resetting signal 1411 is a resetting signal generated when reset switch 1406 is operated.
When CPU 1401 is to be started based on the normal monitoring of the power supply voltage such as when the power supply is turned on, resetting unit 1402 generates CPU resetting signal 1409 and address decoder resetting signal 1410. ROM 1404a is selected, and CPU 1401 executes the boot program stored in ROM 1404a. 
When reset switch 1406 is operated, on the other hand, resetting unit 1402 generates CPU resetting signal 1409 and address decoder resetting signal 1411. CPU 1401 is started in the same manner as when the power supply is turned on. Address decoder 1403 converts addresses generated by CPU 1401, and generates chip select signal 1412b for ROM 1404b which is mapped next to the ordinary boot ROM 1404a. CPU 1401 is then started by the boot program stored in ROM 1404b. Thereafter, each time reset switch 1406 is operated to generate address decoder resetting signal 1411, address decoder 1403 successively changes over chip select signals 1412a through 1412d for the boot addresses.
With the conventional arrangement shown in FIG. 2, as described above, each time reset switch 1406 is operated, one of four ROMs 1404a through 1404d is selected, and the boot program stored therein is used to start CPU 1401.
FIG. 3 of the accompanying drawings shows in block form a conventional boot program rewriting device disclosed in Japanese laid-open patent publication No. 2000-293376. The conventional boot program rewriting device shown in FIG. 3 has CPU 1501, selector 1502, and boot ROMs 1503, 1504. Selector 1502 has switching selector 1508 and offset register 1509. Two boot ROMs 1503, 1504 which are connected to address and data lines 1505 of CPU 1501 have respective storage capacities that are equal to each other.
For starting CPU 1501, selector 1502 decodes an address signal and selects boot ROM 1503 or boot ROM 1504. Boot ROMs 1503, 1504 store respective boot programs each including a check sum and a time stamp. These boot programs include a program of comparing the time stamps of programs written in boot ROMs 1503, 1504. The boot programs also include a process which enables the time stamp to determine whether the check sum of a new program is normal or not.
Switching register 1508 stores the address of a selected boot ROM. Offset register 1509 stores the offset of the other boot ROM with respect to the address of the selected boot ROM which is stored in switching register 1508.
On an address map, the boot program stored in the boot ROM set in switching register 1508 is written in an area “ROM space”, and the boot program stored in the other boot ROM is written in an area “ROM space+offset”. It is assumed that boot ROM 1503 is set in switching register 1508, boot ROM 1504 is set in offset register 1509, and the latest boot program to be used is stored in boot ROM 1504.
When CPU 1501 is to be started, it specifies the address of boot ROM 1503 and executes the boot program stored therein. By executing the boot program, CPU 1501 compares the time stamps of ROM 1503 and ROM 1504 and calculates the check sum of a newer program. If the check sum indicates no error, then CPU 1501 changes the data in switching register 1508 and offset register 1509 in order to set the address of offset ROM 1504 in switching register 1508. When boot ROM 1503 and boot ROM 1504 are changed over, selector 1502 outputs resetting signal 1510 to CPU 1501. Therefore, since boot ROM 1503 and boot ROM 1504 are changed over only when a new boot program is properly written, the writing of a new boot program does not fail, and the startup of CPU 1501 is prevented from failing when the data is broken.
With the cellular phone unit shown in FIG. 1, CPU 1311 cannot be restarted properly if the boot program stored in ROM 1312 is broken or the rewriting of the boot program fails. If such a problem occurs, then it has been customary to remove ROM 1311, rewrite the boot program in ROM 1311 with another device, install ROM 1311 again, and restart CPU 1311. However, such a process has been tedious and time-consuming. Particularly, since the cellular phone unit is manufactured and shipped in a large quantity, the whole rewriting process is likely to be enormous. Another problem is that when the boot ROM is removed, the boot ROM itself and other nearby parts may possibly be damaged.
With the boot program rewriting devices disclosed in Japanese laid-open patent publications Nos. 8-179937 and 2000-293376, it is not necessary to remove the ROM and write the boot program stored therein even when the boot program is broken or the rewriting thereof fails.
However, since a plurality of ROMs or boot program storage areas are required for one CPU, the disclosed boot program rewriting devices are large in scale, and are not preferable for use in cellular phone units which are strongly demanded to be small in size and weight and low in cost. The problem of an increased device scale manifests itself particularly with respect to cellular phone units having two CPUs.